A hardware/software co-design approach to prototype 6G mobile applications inside the GNU Radio SDR Ecosystem using FPGA hardware accelerators
Christian Karle, Marius Kreutzer, Johannes Pfau, Jürgen Becker · 2022
The novel communication 6G requires raw data rates of up to 400 Gbit s− 1 in a single Field Programmable Gate Array (FPGA) front-end. For these high data rates, a Software Defined Radio (SDR) on a multi-core processor reaches a performance limit due to technical boundaries, clock speeds and overhead in multiprocessing. Hence, additional hardware accelerators based on Application Specific Integrated Circuits (ASICs) or FPGAs are required to process those large amounts of data. In this paper, our hardware/software co-design concept is presented, which allows for the integration of hardware accelerators realized in FPGAs, to improve overall system performance. We can access the accelerators from the widely used GNU Radio, which also allows non-FPGA user to benefit from the acceleration. For this purpose, a concept to share data between Processing System (PS) and Programmable Logic (PL) is developed and evaluated regarding its suitability for high bandwidth applications. Using a common application for evaluation, we are able to compare a hardware/software co-design with an entirely software-based implementation. Resulting in an overall performance increase by a factor of up to 4.5, while serving as a foundation for an easy-to-use method for hardware accelerators in GNU Radio.