ASIC and FPGA Implementation of a Novel BCSE Algorithm based Reconfigurable FIR Filter for Low Power applications
M Jagadeeswari, S. Padmapriya, M Selvaganesh · 2022 8th International Conference on Advanced Computing and Communication Systems (ICACCS) · 2022
The paper focusses on an efficient reconfigurable Finite Impulse Response Filter (FIR) design based on the sub-expressions for low power applications. The reversible gates are used instead of the logic gates for the design of an efficient low power reconfigurable filter. Across the adjacent coefficients, sub-expression elimination and the variable sub-expression elimination were applied within each coefficient. The proposed Reversible Binary Common Sub-Expression Elimination (BCSE) algorithm is implemented in FPGA and also in Cadence EDA tool. The results shows that, the proposed algorithm power consumption is reduced by 140558.856 nano watts along with an improvement in the Power saving ratios to 7.6%, 20.6% and 28% with the existing techniques respectively.