Memory and Energy Efficient Memory Model and Instruction Set Architectures for Tree Data Structures
Mouad Rifai, Lennart Johnsson · 2022
In general, data structures incorporating significant numbers of memory address pointers needlessly occupy large areas of dynamic memory. Moreover, packed binary data structures suffer from slow access time caused by unpacking and repacking. To address these issues and improve power and energy efficiency, we have designed a special memory model and instruction set architectures (ISA) for it. Our Random-Bit-Vector-Access Memory (RBVAM) together with Flexible-Width Data Computer (FWDC) ISA family enable access to and computation on data whose bitwidth is software specified, effectively eliminating packed binary data structure access overhead. The FWDC ISA family is inspired by the RISC-V’s RV32 ISA but tailored for RBVAM. We investigate a 32-bit and a 24-bit FWDC and propose a microarchitecture that implements them on an FPGA. For voxelized 3D point-cloud indexing, a RBVAM in combination with a FWDC ISA can achieve about 5 × energy savings merely from the reduced physical memory space requirements, and about 5 × energy savings compared to conventional memory models used with a RISC-V core.