Area efficient 2D FIR filter architecture for image processing applications
Soumica Cheemalakonda, Sudeeksha Chagarlamudi, Bhasita Dasari, Shaik Sameena Sulthana, Kishore Kumar Gundugonti · 2022 6th International Conference on Devices, Circuits and Systems (ICDCS) · 2022
The 2D- finite impulse response filters are efficient and are of low complexity and they are often used for image restoration, image enhancement and denoising applications. The 2D FIR filter architecture usually includes multipliers which are implemented using network of adders/ subtractors and shifters, which can be further optimized. In this study, an area efficient 2D FIR filter architecture is implemented using Radix -2rmultiplication which reduces the no. of partial products, reduces the no. of multipliers and thus optimizes area. This symmetric filter is implemented in gatelevel Verilog HDL for three kernel sizes, 3x3,5x5 and 7x7, in direct form architecture. Intel DSP Builder is used to check the proposed filter’s functionality and synthesis is carried out using Intel Quartus Standard edition. When the FPGA results of hardware resources used are compared to previous works, it is discovered that the proposed filter takes up less space for different kernel sizes.