ASIC Implementation of Hardware Efficient DTCWT Architecture for Intra Prediction HEVC Coding in Complex Wavelet
Virupakshi Madhurima, K. Padmapriya · Ingénierie des systèmes d information · 2022
Hardware efficient DTCWT architecture for intra prediction coding that is designed using systolic array algorithm is presented in this work.In order to have a trade-off between computation complexity and latency systolic array based architecture is designed for DTCWT computation.Design of optimum structure for systolic array algorithm is presented.Parallel processing of the input images considering multiple rows and columns is designed to accelerate the throughput.The systolic array structure design presented in this work is for multiplying matrix of 6 x 6 and 6 x 4 elements.The data control unit provides synchronization of information flow in both the SAA structures.The design is synthesized in the Cadence environment, post place, map and route simulation also have been carried out.Tables in the text summarizes the initial estimation of area performances for the four different timing constraints set.The maximum operating frequency is identified to be of 300 MHz and the power dissipation is limited to less than 3 mW at 2.0 V power.Further optimization in the design metrics can be achieved by increasing the number of frames to be processed.