An Efficient Architecture and High-Throughput Implementation of CCSDS-123.0-B-2 Hybrid Entropy Coder Targeting Space-Grade SRAM FPGA Technology
Panagiotis Chatziantoniou, Antonis Tsigkanos, Dimitris Theodoropoulos, N. Kranitis, Antonis Paschalis · IEEE Transactions on Aerospace and Electronic Systems · 2022
Nowadays, hyperspectral imaging is recognized as cornerstone remote sensing technology. The explosive growth in image data volume and instrument data rates, compete with limited on-board storage and downlink bandwidth, making hyperspectral data compression a mission critical task. Recently, the consultative committee for space data systems (CCSDS) extended the previous issue of the CCSDS-123.0 Recommended Standard for multi/hyperspectral image compression to provide Near-Lossless compression functionality. A key feature of the CCSDS-123.0-B-2 is the improved Hybrid Entropy Coder providing substantially better compression performance than the Issue 1 entropy coders at low bit rates. In this paper, we introduce a high-throughput hardware implementation of the CCSDS-123.0-B-2 Hybrid Entropy Coder. The introduced architecture exploits the systolic design pattern providing modularity and latency insensitivity in a deep and elastic pipeline, achieving constant throughput of 1 sample/cycle with small field programmable gate array (FPGA) resource footprint. This architecture is described in portable VHDL register-transfer level (RTL) and implemented, validated and demonstrated on a commercially available Xilinx KCU105 development board hosting a Xilinx Kintex Ultrascale XCKU040 SRAM FPGA, and thus, is directly transferable to the Xilinx Radiation Tolerant Kintex UltraScale XQRKU060 space-grade devices. Moreover, state-of-the-art SpaceFibre (ECSS-E-ST-50-11C) serial link interface and test equipment were used in the validation platform to emulate an on-board deployment. The introduced CCSDS-123.0-B-2 Hybrid Entropy Coder achieves a constant throughput performance of 305 MSamples/s. To the best of our knowledge, this is the first published fully-compliant architecture and high-throughput implementation of the CCSDS-123.0-B-2 Hybrid Entropy Coder, targeting space-grade FPGA technology.