Design and Performance Analysis of Various 32-bit Hybrid Adders using Verilog
R Renjith, Benson Biju, Ancy Joy, Vaishnavi Ganeshan, R Sivasankar · 2022 IEEE International Conference on Signal Processing, Informatics, Communication and Energy Systems (SPICES) · 2022
Area, Power and Delay optimizations are the challenges in current digital IC design. Processors which are being currently used require adder units. In this work, different type of 32-bit VLSI adders will be studied and their design implementation will be done. Some of the adders were designed using 3-2 compressor. Some of the 32-bit hybrid adders is proposed by using differing types of combination of adders and logic. The combination includes parallel prefix adders like Kogge-Stone adder (KSA), Brent-Kung adder (BKA), Ladner-Fischer adder (LFA) and Han-Carlson adder (HCA). Two 64-bit hybrid adders is designed by analyzing the performance of the 32-bit designed hybrid adders and by selecting the best 32-bit adders. Analysis of the adder performance can be done in terms of Area (Number of LUT s), Delay (nS) and Power (W) analysis is performed with the help of Xilinx ISE 14.7, a Verilog synthesis software and implementation of the same using Verilog HDL family Spartan-6 selecting device XC6SLX16 choosing grade speed -3.