Systolic architectures for finite-state vector quantization
R.K. Kolagotla, S.-S. Yu, J. JaJa · 2003
The authors present a new systolic architecture for implementing finite state vector quantization in real-time for both speech and image data. This architecture is modular and has a very simple control flow. Only one processor is needed for speech compression. A linear array of processors is used for image compression; the number of processors needed is independent of the size of the image. Image data is processed at a rate of 1 pixel per clock cycle. An implementation at 31.5 MHz can quantize 1024*1024 pixel images at 30 frames/sec in real-time. The authors describe a VLSI implementation of these processors.>