An 8-way VLIW embedded multimedia processor built in 7-layer metal 0.11 /spl mu/m CMOS technology
H. Okano, Atsuhiro Suga, T. Shiota, Y. Takebe, Y. Nakamura, N. Higaki, H. Kimura, H. Miyake, Tohru Satoh, K. Kawasaki, R. Sasagawa, W. Shibamoto, M. Sasaki, N. Ando, T. Yamana, Isao Fukushi, S. Tago, F. Hayakawa, T. Kamigata, S. Imai · 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) · 2002
A 533 MHz 2.5 W 2132 MIPS 12.8 GOPS 2.1 GFLOPS 8-way VLIW embedded multimedia processor occupies a 7.8/spl times/7.8 mm/sup 2/ die in a 7-layer metal 0.11 /spl mu/m CMOS at 1.2 V. VLIW, SIMD, dynamic branch prediction, non-aligned dual load/store mechanism and a crosstalk-aware design flow contribute to performance.