Hierarchical top-down layout design method for VLSI chip
Tohru Adachi, Hitoshi Kitazawa, Mitsuyoshi Nagatani, T. Sudo · 1982
A new hierarchical top-down layout design system for custom VLSIs has been developed. A top-down global route assignment process reduces the redundant wiring area. Routing in a single path over the whole chip enables efficient chip area use.