A register-transfer-level fault simulator for permanent and transient faults in embedded processors
C. Rousselle, M. Pflanz, A. Behling, T. Mohaupt, H.T. Vierhaus · 2002
HEARTLESS (Hierarchical Register-Transfer-Level Fault-Simulator for Permanent & Transient Faults) was developed to simulate the behavior of complex sequential designs like processor cores in case of transient and permanent faults. HEARTLESS can be enhanced by propagation over macros described in a C++ function. Available is a C-interface for access to internal signals during the simulation.