A high-speed residue-to-binary converter for three-moduli (2/sup k/, 2/sup k/-1, 2/sup k-1/-1) RNS and a scheme for its VLSI implementation
Wei Wang, M.N.S. Swamy, M.O. Ahmad, Yuke Wang · IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing · 2000
In this paper, a high-speed residue-to-binary converter for the moduli set (2/sup k/, 2/sup k/-1, 2/sup k-1/-1) is proposed. Compared to the previous converter based on this moduli set, the proposed one is 40% faster. Also, the time-complexity product is improved by 20%. Following the top-down very large scale integration design flow, the proposed converter is implemented in 0.5 micron CMOS technology. Based on this moduli set, layouts of the 8-, 16-, 32-, and 64-bit residue-to-binary converters, which can be used in further residue number system designs, are generated and simulation results obtained.