Towards formal verification on the system level
R. Drechsler · 2004
Due to increasing design complexity and intensive reuse of components, verifying the correctness of circuits and systems becomes a more and more important factor. In the meantime, in many projects up to 80% of the overall design costs are caused by verification and by this, checking the correct behavior becomes the dominating factor. Formal verification has been proposed as a promising alternative to simulation and has become a standard in many flows. In this paper, existing approaches are reviewed and recent trends for system level verification are outlined. To demonstrate the techniques SystemC is used as a system level description language. Beside the successful applications a list of challenging problems is provided. This gives a better understanding of current problems in hardware verification and shows directions for future research.