Design considerations for a bipolar implementation of SPARC
Ar. Shriya Agrawal, Emil W. Brown, Joseph Petolino, James R. Peterson · 1988
The design of Sun Microsystems' Scalable Processor Architecture (SPARC) using bipolar emitter-coupled-logic (ECL) process is considered. The BIT1 ECL process and design considerations for an ECL implementation of SPARC are described. Bus structures, cache concerns, interface considerations, and power density are discussed.>