Automated Pipelining for Clocked CMOS Logic and FPGAs
Thomas Pepler · 2016
Achieving multi-Gbps clock speeds with static CMOS logic requires migrating designs to smaller geometries, which present a higher development and fabrication cost.Instead, this research investigates the use of clocked CMOS logic to create an inherently pipelined circuit that can be clocked up to 2.5x faster than the standard cells available in the IC design kit.An algorithm was developed and implemented in Perl to process Verilog RTL netlists for compatibility with the clocked logic.As an example application, a cascaded integrator comb (CIC) filter for RF DSP was designed with the clocked CMOS and fabricated in the IBM 130 nm process.Unfortunately, due to an oversight with designing the boundary scan chain, true functionality of the circuit could not be verified.In another demonstration of concept, the algorithm was successfully applied to a QAM modulator design on a Xilinx Virtex-5 FPGA, which achieved a clock speed of 548 MHz.First, I would like to acknowledge my supervisor Prof. Calvin Plett, who supported me throughout this research and provided insightful comments on this thesis.As well, a large thank you goes to Mr. Yatish Kumar, who provided the initial concepts for this research, gave much-needed guidance on the technical issues, and proved to be a valuable mentor to me.I am also grateful to Prof. Ryan Griffin and Mr. Stephen Toth for helping