A 1.8 V 700 Mb/s/pin 512 Mb DDR-II SDRAM with on-die termination and off-chip driver calibration
C. Yoo, K. Kyung, G.-H. Han, K. Lim, H. Lee, J. Chai, N.-W. Heo, G. Byun, Deok-Hee Lee, H.-I. Choi, H.-I. Choi, Chungman Kim, S. Cho · 2003
A 1.8 V 700 Mb/s/pin 512 Mb DDR-II SDRAM is JEDEC standard compliant. With the hierarchical I/O line and local sensing, t/sub AA/ /t/sub RCD//t/sub RP/ of 3/3/3 at 533 Mb/s are achieved in the design. For signal integrity at 533 Mb/s, off-chip driver calibration and on-die termination are employed.