A 1.6 GB/s data-transfer-rate 8 Mb embedded DRAM
S. Miyano, K. Numata, K. Sato, T. Yabe, M. Wada, Ryousuke HAGA, M. Enkaku, M. Shiochi, Y. Kawashima, M. Iwase, Masahisa Ohgata, J. Kumagai, T. Yoshida, M. Sakurai, S. Kaki, N. Yanagiya, H. Shinya, Tohru Furuyama, P. Hansen, M. Hannah · 2002
To realize high data-transfer rate in random access, several kinds of DRAMs with on-chip cache memory have been proposed. These DRAMs rely on locality of access to achieve the highest speed. However, in some graphic applications where sufficient locality of access is not expected, such DRAMs will not greatly accelerate system performance. Embedded memories have benefits for such applications due to their wide data bus and band width. The 8 Mb embedded DRAM presented in this paper provides 1.6 GB/s data transfer rate and realizes 10 ns cycle random access without page fault delay.