Implementation of a linear histogram BIST for ADCs
Florence Azais, Serge Bernard, Y. Bertrand, M. Renovell · 2002
This paper validates a linear histogram BIST scheme for ADC testing. This scheme uses a time decomposition technique in order to minimize the required hardware circuitry. A practical implementation is described and the structure together with the operating mode of the different modules are detailed. Through this practical implementation, the performances and limitations of the proposed scheme are evaluated both in terms of additional circuitry and test time.