Toward Bug-free Multicore SoC Architectures: System Validation with Transaction-Level Models
IEEE Design & Test of Computers · 2011
This theme issue brings to D&T readers important recent advances in functional verification of multicore SoC architectures using transaction-level models. Such a system-level approach is advocated to manage verification complexity and catch bugs early in the design cycle, so that the potential of multicore architectures can be realized for higher performance, power management, and functional diversity. Also in this issue are two features on testing and fault tolerance.