Petaflops Basics - Performance from SMP Building Blocks Christian Bischof, Dieter an Mey, Christian Terboven, and Samuel Sarholz
2007
Christian Bischof Institute for Scientific Computing and Center for Computing and Communication RWTH Aachen University [email protected] Dieter an Mey Center for Computing and Communication RWTH Aachen University [email protected] Christian Terboven Center for Computing and Communication RWTH Aachen University [email protected] Samuel Sarholz Center for Computing and Communication RWTH Aachen University [email protected] The number of processor cores in commodity architectures and in particular in the nodes of high-end computers is increasing. Today only few architectures in the current TOP500 list, like the IBM Blue Gene/L and some of the Cray XT3 systems, employ nodes which are restricted to the MPI-only parallelization paradigm. But IBM is building its petaflop machine in the context of the DARPA High Productivity Computing Systems (HPCS) program based on Power7 processors [28] and Cray is already providing dual-core Opteron processors for its leading edge systems.