DIAGNOSTIC PORT FOR SCANNING THE SELECTED OBJECTS IN THE ELECTRONIC MEANS ON FPGA
В. А. Коковин, Saygid U. Uvaysov · Kontrol Diagnostika · 2015
AN 39: IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera DevicesAltera devices either have pins dedicated for IEEE Std.1149.1 operation or the IEEE Std.1149.1 pins are dual purpose; they can either be used for JTAG only or as regular I/O pins.For the families that support it, you can use the four JTAG pins as I/O pins by turning off the JTAG option with the MAX+PLUS ® II or Quartus ® II software (see "Enabling IEEE Std.1149.1 BST Circuitry" on page 32 of this application note).Go to the appropriate device family data sheet for specific information on device and package combinations.The IEEE Std.1149.1 BST circuitry requires the following registers: ■ The instruction register, which is used to determine the action to be performed and the data register to be accessed.■ The bypass register, which is a 1-bit-long data register used to provide a minimum-length serial path between TDI and TDO.■ The boundary-scan register, which is a shift register composed of all the BSCs of the device.