Heterogeneous programmable logic block architectures
Aneesh Koorapaty, V. Chandra, K. Y. Tong, C. Patel, Larry Pileggi, Herman H. Schmit · 2003
In this paper we propose four new heterogeneous programmable logic blocks (PLBs) consisting of a combination of various sizes of look up tables (LUTs), multiplexers (MUXes), and logic gates. We demonstrate that these PLBs offer significant performance and density benefits over more homogeneous PLBs.