An acoustic echo canceler
Wei‐Chih Hsu, F. Chui, D.A. Hodges · 2003
The authors describe an experimental 1000-tap, single-chip, programmable acoustic echo canceler designed in a 3- mu m, double-metal, p-well, CMOS technology. Hardware minimization is considered from both the system and the architecture perspective. To implement more simply an echo-canceler chip with 1000 taps, floating-point representations for both data and coefficients are used to accommodate the wide dynamic range of the speech signal (6 mantissa bits for the data, 14 mantissa bits for the coefficients, and 3 exponent bits for each). Required memory is reduced from 34 kb to 26 kb. The data paths for adaptation and convolution are designed with emphasis on regularity and modularity. The echo return loss and the convergence performance of a prototype operating at 1000 taps are shown.>