Exploring concurrency in data path functional units BIST plan optimization: a study-case
J. Amazonas, M. Strum, Wang Jiang Chau · 2002
This paper presents a procedure to optimize the parallel test plan of all functional units present in a data path. Our algorithm defines which registers will be transformed into test pattern generators (TPGs) and signature analyzers (SAs), minimizing a test cost function. Cellular automata (CAs) registers will be used both for TPG and SA. Very good results were obtained for the tested architectures. A comparison between the parallel test and a serial test has shown a large test time reduction with a small hardware penalty. This procedure is part of an ongoing research which consists of the development of tools to automatically generate BIST testable circuits for architectures synthesized by the MACH high-level synthesis system.