Guest Editorial Special Section on Configurable Computing Design—II: Hardware Level Reconfiguration
Toomas P. Plaks · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2008
The eight papers in this special section address the issue of configurable computing design. These papers focus on hardware level problems: how to build efficient gate arrays; security and fault tolerance issues on configurable hardware; and implementing floating-point arithmetic and specific decoders on field-programmable gate arrays (FPGAs).