Hierarchical Design Verification for Large Digital Systems
T. Sasaki, A. Yamada, T. Aoyama, K. Hasegawa, S. Kato, S. Sato · 18th Design Automation Conference · 1981
This paper describes a hierarchical design verification system, consisting of a logic verification subsystem, MIXS(1), a timing verification subsystem, NELTAS(2), and a hierarchical data base. MIXS is a mixed level simulator, which can handle both functional and chip or gate level models with a unified simulation mechanism based on "node" model concept. NELTAS analizes delay time by tracing logical paths and calculating their media delay time. Both subsystems have hierarchical processing capability.