Clip: An Optimizing Layout Generator For Two-dimensional Cmos Cells
Arushi Gupta, John P. Hayes · 2005
We present a novel technique CLIP for optimizing both the height and width of CMOS cell layouts in the two-dimensional (2D) style. CLIP is based on integer-linear programming (ILP) and proceeds in two stages: First, an ILP model is used to determine a 2-D layout of minimum width W cell . Then, another model generates a 2-D layout that has width W cell and requires a minimum number of routing tracks. Run times are in seconds for circuits with up to 16 transistors. For larger circuits, we extend CLIP to a hierarchical method HCLIP that places series-connected transistors contiguously. This reduces run times by up to three orders of magnitude, and still yields optimal results in over 80% of cases. 1 Introduction The objective of cell layout synthesis is to minimize the cell area subject to constraints. For one-dimensional (1-D) layouts, which use a single pair of parallel P and N diffusion rows, minimizing both cell width and height can yield up to 80% savings in area over width minimiz...