Design of Low Power RSC Encoder Using Reversible Logic
J. Aishvarya, P. S. N. V. V. Sai Manindra, P. Sathya Priya, Kruthi Vaseeshwar Rao, E Prabhu · 2018 International Conference on Inventive Research in Computing Applications (ICIRCA) · 2018
The main focus in present world of electronics is designing low power circuits. In modern technologies, low power design has drawn significant concern due to increasing transistor counts, higher speed of operations and clock frequencies. Reversible logic plays an important role when VLSI circuits with minimal power dissipation are considered. It has the capacity to decrease the power dissipation by recuperating bit loss from its distinctive one to one mapping. A novel design of Recursive Systematic Convolutional (RSC) Encoder using the existing reversible gates is presented in this paper. The proposed RSC encoder is coded in Verilog-HDL and synthesized in synopsis DC tool (90nm library). The power analysis report shows that the proposed RSC encoder circuit dissipates less power when compared to the conventional one.