An efficient embedded bitstream parsing processor for MPEG-4 video decoding system
Yung‐Chi Chang, Chao-Chih Huang, Wei-Min Chao, Liang‐Gee Chen · 2004
In this paper, the bitstream parsing analysis and an efficient and flexible bitstream parsing processor are presented. The bit-stream parsing analysis explores the critical part in bitstream parsing. Based on the result, the novel approaches to parse data partitioned bitstreams are presented. An efficient instruction set optimized for bitstream processing, especially for DCT coefficient decoding, is designed and the processor architecture can be programmed for various video standards. It has been integrated into an MPEG-4 video decoding system successfully and can achieve real time bitstream decoding with bitstream coded under 4CIF frame size with 30 fps, 8Mbps, which is the specification of MPEG-4 Advanced Simple Profile Level 5.