Implementation of a third-generation 1.1GHz 64b microprocessor
G. Konstadinidis, Kevin Normoyle, S. Wong, S. Bhutani, Harry Stuimer, T. Johnson, A. Smith, D. Cheung, F. Romano, Shifeng Yu, Sung-Hun Oh, Victor Melamed, S. Narayanan, D. Bunsey, C. Khieu, K.J. Wu, R. Schmitt, A. Dumlao, M. Sutera, J. Chau · 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) · 2002
A third-generation 1.1 GHz 64b microprocessor provides 1 MB on-chip L2$, 4GB/s off chip memory bandwidth and a 200MHz JBUS interface that supports 1 to 4 processors. The 90M transistor chip is implemented in a 7-level metal copper 0.13/spl mu/m CMOS process and dissipates 53W at 1.3V and 1.1GHz.