Reversible Counter, Decoder, and Encoder Circuits
Hafiz Md. Hasan Babu · 2020
This chapter describes a design of n-bit reversible counter, the reversible decoder without enable input, and reversible encoder. It presents designs for both the asynchronous counter and the synchronous counter. While designing counter, the chapter also describes the design of reversible T flip-flop, which is the building block of the counter circuit. It presents the design of T flip-flop, gated T flip-flop, and master–slave T flip-flop. The quantum implementation of a reversible circuit, which is configured as a reversible 2–to–4 decoder. The design of a reversible 2–to–4 decoder reversibly generates all four necessary AND functions using a single Fredkin gate and minimal supplementary logic. The reversible 4–to–2 encoder design assumes – like traditional encoders – that exactly one of its four inputs will have an input value of logical 1 at any time.