Design And Enactment Of Dynamically Reconfigurable Bus Enhanced Noc Architecture For Emerging Digital System
A. Mariyammal, J. Rajprabha, A. Sountharyabanu, N. Sangavi, G Malarvizhi · International Journal of Engineering and Advanced Technology · 2019
The large amount imperative issue in present VLSI circuit proposes in the area and power reduction. This work proposes a new architecture which reduces an area efficiently.The reimbursement of adding a little latency, modified mutual bus as an essential element of the NoC structural design is explored. This architecture design reduces the charge of partisan a broad choice of design occurrence through specified throughput needs by minimizing the requirement of design entities in the architecture design of NoC road and rail network for the area minimization.