A fast hierarchical arbitration scheme for multi-tb/s packet switches with shared memory switching
D. Popa, Georg Post, Ludovic Noirie · Bell Labs Technical Journal · 2009
One challenge in multi-terabit per second packet switches is the design of low latency and high performance arbitration schemes. In this regard, we propose a hierarchical multi-cell arbiter, which interconnects multiple parallel processing devices. By comparison with iterative non-hierarchical multi-cell arbiters, we show that our scheme significantly decreases the signaling overhead and arbitration processing time. Performance evaluation results show the proposed solution maximizes the switch throughput and delay performance.