Area and power reduction of embedded DSP systems using instruction compression and re-configurable encoding
S.G. Chandar, M. Mehendale, R. Govindarajan · 2002
Proposes a run-time reconfiguration mechanism to map multiple instructions on a single compressed bit pattern, thus enabling significant code compression. This results in reduced area due to smaller program memory size and also reduces instruction fetch related power dissipation. We enhance Texas Instruments DSP core TMS320C27x to incorporate this mechanism and evaluate the improvements on code size and instruction fetch energy using real life embedded control application programs. We show that with minimal hardware overhead, we can reduce code size by over 10% and instruction fetch energy by over 40%.