VLSI-placement based on routing and timing information
J. Garbers, B. Korte, H. J. Prömel, E. Schwietzke, A. Steger · Proceedings of the European Design Automation Conference, 1990., EDAC. · 2002
The authors propose a hierarchical placement procedure incorporating more and more detailed routing and timing information at increasing levels of the hierarchy. This procedure is based on the well-known min-cut method. A global routing and a timing analysis are computed after every cut and are used to guide the subsequent cell partitioning.>