A simple algorithm for fanout optimization using high-performance buffer libraries
K.L. Kodandapani, J. Grodstein, A. Domic, H. Touati · 2002
We present an algorithm for computing minimal-area fanout networks satisfying a delay constraint. We focus on one type of fanout network structure, the fanout chain. We show that, when using libraries designed for high-speed custom CMOS chips, the fanout chain typically produces minimal-area fanout networks for a given delay constraint. We then present fast, near-optimal algorithms to compute these fanout structures.