An improved high-level built-in self-test synthesis algorithm
2001
In this paper, we describe an improved high-level built-in self-test synthesis algorithm for operation scheduling and data path allocation. It generates highly self-testable data path design while maximizing the sharing of test registers, which means only a small number of registers is modified for BIST. The algorithm also produces design with high test concurrency, thereby decreasing test time. In our previous work (Yang and Muzio, 2001), we have proposed an integrated operation scheduling and data path allocation approach for built-in self-testable designs. In this study, we mainly make use of some concepts and techniques to improve the previous work during the operation scheduling part, especially to determine the execution order of different operations when rescheduling transformations are performed. With a variety of benchmarks, we demonstrate the advantage of our approach compared with other conventional approaches.