Reversible Programmable Logic Devices
Hafiz Md. Hasan Babu · 2020
This chapter introduces an approach of designing reversible programmable logic arrays, anmely, reversible field programmable gate array (FPGA) and reversible programmable logic array (PLA). It describes the reversible architecture of logic elements of Plessey FPGA. The reversible architecture is designed using reversible multiplexer, D latch, NAND, and a reversible random access memory. The chapter discusses the design of reversible PLA, which enables realization of multi-output exclusive-OR sum-of-product (ESOP) functions by using a reversible gate called multiplexer gate. It introduces an algorithm to calculate the critical path delay of reversible PLAs. The chapter explains the calculation of the delay of reversible PLAs in a greedy approach. The calculation is divided into two phases: AND plane delay and Ex-OR plane delay. Some properties on the numbers of gates, garbages, and quantum costs of reversible PLAs are also shown.