Test generation for multiple faults based on parallel vector pair analysis
S. Kajihara, T. Sumioka, K. Kinoshita · 2002
This paper presents a method for generating test sets to detect multiple stuck-at faults in combinational circuits. The proposed method is based on parallel vector pair analysis which finds faulty status of each line. The parallel analysis can bring higher fault coverage and smaller test sets than the serial vector pair analysis. In our method, redundant lines are removed firstly. An then a compacted test set for single stuck-at faults is generated in order to construct vector pairs used in the parallel analysis. Experimental results show that test sets to detect all multiple stuck-at faults were generated for 25 benchmark circuits and the parallel analysis was very effective for test generation.