Solution of the Three-Dimensional Finite Difference Equations Using Parallel Reconfigurable Hardware Accelerators
E.J.C. Stewart, Jinyu Hu, S.F. Quigley, Andrew H. C. Chan · Civil-comp proceedings · 2009
This paper describes a study of the use of FPGA-based reconfigurable hardware, in the form of a coprocessor within a standard PC, to accelerate a solution of the 3-D finite difference formulation of the Laplace equation. The domain decomposition and solution approach are formulated so as to make maximum use of the parallelism within the FPGA, and to minimize limitations imposed by I/O bandwidth between the FPGA and the computer memory. The resulting system provides a red-black SOR solver that can achieve a speed-up of approximately 50 compared to a fast PC.