Reversible Fault‐Tolerant Multiplier Circuit
Hafiz Md. Hasan Babu · 2020
This chapter presents an optimal methodology for designing a fault-tolerant reversible multiplier. It provides algorithms to construct the partial product generation circuit and the multi-operand addition circuit of the multiplier. The chapter describes a fault-tolerant reversible gate, namely, LMH gate, to produce an optimal multiplier. There are several reversible fault tolerant multipliers available in the market. One available multiplier uses Fredkin gate for partial product generation and islam gate for multi-operand addition. Another available multiplier uses Fredkin gate for partial product generation. It also uses one modified islam gate (MIG) as half adder and two modified islam gates as full adder. Several theorems on the numbers of gates, garbage outputs, and quantum cost of the fault-tolerant reversible multiplier are presented to show its optimality.