Formal verification of timing conditions
H. Eveking, C. Mai · Proceedings of the European Design Automation Conference, 1990., EDAC. · 2002
Most timing-verifiers are analytical tools that determine, e.g., the delays on all paths, etc. This paper presents a completely different approach: timing-verification is performed by means of the formal transformation of CHDL descriptions. The principles of this procedure are presented and performance results of an implementation are given.>