Functional verification of system on chips - practices, issues and challenges
S.K. Roy, S. Ramesh · Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design · 2003
Summary form only given. In a complex SoC design flow functional verification is very important; any behavioral or functional bug escaping this phase will not be detected in the subsequent implementation phases and will surface only after the first silicon is integrated into the target system, resulting in costly design and silicon iterations. A number of academic and industrial research laboratories have been carrying out research on functional verification of SoCs based on different approaches. Many of the issues relate to intrinsic limitations of some of the approaches taken; while others have to do with the quality of the design information, by way of design descriptions, design documentations and design specifications, from which the overall verification objectives are derived. SoCs have brought to focus the need to carry out design and verification concurrently. For the design and verification task to proceed concurrently there is a need to capture formally, design information and implementation details at various levels of abstraction. As designs become more complex, functional verification will have to be carried out using the divide and conquer approach. We discuss several approaches based on compositional verification.