Design and implementation of single precision floating point multiplier using vhdl on spartan
International Journal of Latest Trends in Engineering and Technology · 2017
Floating point multipliers have variety of applications in fields like finance, medical imaging, biometrics, high performance audio etc. and also Multipliers play a key role in microprocessors, DSP processors and various FIR filters.A performance of a system is generally determined by the performance of the multiplier because the multiplier is generally the slowest element in the system.Since multiplication dominates the execution time of most DSP application so there is need of high speed multiplier.Hence increasing the speed and optimizing area of the multiplier is a major design issue.This work deals with the design and implementation of optimized floating point multiplier.IEEE 754 single precision format is used to represent floating point numbers.The general representation of floating point number is: (-1) ^S h 1.F h 2^ (E-127), where the range of E is -126 to +127. II. IMPLEMENTATION OF FLOATING POINT MULTIPLIER