Unleashing the high-performance and low-power of multi-core DSPs for general-purpose HPC
Francisco D. Igual, Murtaza Ali, Arnon Friedmann, Eric J. Stotzer, Timothy Wentz, Robert A. Geijn · 2012 International Conference for High Performance Computing, Networking, Storage and Analysis · 2012
Take a multicore Digital Signal Processor (DSP) chip designed for cellular base stations and radio network controllers, add floating-point capabilities to support 4G networks, and out of thin air a HPC engine is born. The potential for HPC is clear: It promises 128 GFLOPS (single precision) for 10 Watts; It is used in millions of network related devices and hence benefits from economies of scale; It should be simpler to program than a GPU. Simply put, it is fast, green, and cheap. But is it easy to use? In this paper, we show how this potential can be applied to general-purpose high performance computing, more specifically to dense matrix computations, without major changes in existing codes and methodologies, and with excellent performance and power consumption numbers.