A 60 mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme
Masafumi Takahashi, M. Hamada, T. Nishikawa, Hideho Arakida, Y. Tsuboi, Takeshi Fujita, Fumitoshi Hatori, S. Mita, K. Suzuki, A. Chiba, Toshihiro Terazawa, Fumihiko Sano, Yoshinori Watanabe, Hisayo Sasaki Momose, K. Usami, Mutsunori Igarashi, T. Ishikawa, Masahiro Kanazawa, T. Kuroda, Tohru Furuyama · 2002
This MPEG4 video codec implements essential functions in the MPEG4 committee draft. It consumes 60 mW at 30 MHz, 30% of the power dissipation of a conventional CMOS design. Measured power dissipation is summarized. 70% power reduction is achieved by low-power techniques at circuit and architectural levels. A 16b RISC processor provides software programmability. Binary shape decoding uses 20% of the computation power of the RISC processor at 30MHz clock, with negligible increase in chip power dissipation. Three-step hierarchical motion estimation reduces power dissipation.