The scalable processor architecture (SPARC)
Robert B. Garner, Ar. Shriya Agrawal, F. Briggs, Emil W. Brown, D. Hough, B. Joy, Steve R. Kleiman, Steven S. Muchnick, Masood Namjoo, D. Patterson, J. Pendleton, Richard Tuck · 1988
An introduction is given to the SPARC architecture and its more interesting features. The discussion covers the registers (both window and floating-point), and instructions, including formats, load/store, integer computation, control transfer, floating-point computation, and coprocessor. A brief comparison with Berkeley RISC (reduced-instruction-set-computer) and SOAR is provided.>