Key-based Obfuscation using HT-like Trigger Circuit for 128-bit AES Hardware IP Core
Surbhi Chhabra, Kusum Lata · 2021
System-on-Chip (SoC) architectures based on semiconductor Intellectual Property (IP) cores has become ubiquitous in the today’s era. Protecting these semiconductor IPs from various ill-intention activities like tampering, malicious circuitry alternations or reverse engineering is a huge challenge for semiconductor IP designers. A Novel approach for protecting the Advanced Encryption Standard (AES) 128-bit hardware IP core with key-based obfuscation and Hardware Trojan (HT)-like Trigger circuit at the Register Transfer Level is introduced in this paper, which can be used in re-usable IP core designs. Proposed methodology is implemented on Basys-3 (Artix-7 FPGA) board using Xilinx Vivado 2016.2. Authors can get the successful results for text data encryption and decryption both. The AES IP core simulation results show that with just 2% of the power and area overhead, more security can be achieved. For reducing the attacker’s certainty, we are able to achieve a 40% Avalanche Effect and 50% Hamming Distance. The maximum frequency achieved by the proposed methodology is 373.69 MHz resulting in a throughput of 4.35 Gbps.