Design & Simulation of RISC Processor using Hyper Pipelining Technique
Assistant Professor in HIET (ECE) Shahpur, Distt.-Kangra H.P, INDIA · IOSR Journal of Mechanical and Civil Engineering · 2013
This Hyper pipelining technique is different to the pipelining of instruction decoding known from RISC processors.The point is that we can use hyper pipelining on top of any sequential logic, for example a RISC processor, independent of its underlying functionality.The RISC processor with pipelined instruction set decoding can automatically be hyper pipelined to generate CMF individual RISC processors.Hyper pipelining implements additional register and can use register balancing for fine grain timing optimizations.The method hyper pipelining is also called "C-slow Retiming".The main benefit is the multiplication of the core's functionality by only implementing registers.This is a great advantage for ASICs but obviously very attractive for FPGAs with their already existing registers.