Vertical NAND Flash
Betty Prince · 2014
Several 3D NAND flash arrays are discussed in this chapter including 3D charge-trapping (CT) devices with vertical channel array structure (P-BiCS, VRAT, TCAT, and VNAND) and with vertical gate structure (VG-NAND and VG BE-SONOS). Also discussed are 3D NAND flash arrays with vertical channels and floating gate structure (ESCG, S-SCG, DC-SF, and SCP). An analysis of sub-20 nm scaling trends concluded that planar NAND arrays would prevail until scaling becomes more expensive than vertical structures. The vertical channel gate-all-around (GAA) CT NAND flash bit-cost scalable (BiCS) process technology was described, along with the configuration of the 3D array stack. A pipe-shaped version (P-BiCS) solved the issue of a high-resistance source line. A CT vertical recess array transistor (VRAT) NAND technology was described, which used a vertical pipe substrate with double gates along with a zigzag VRAT (Z-VRAT) that cut the substrate in half and had a single gate on each cell. The vertical stacked array technology (VSAT) used three vertical stacks with eight devices per stack in a gate-first structure. The vertical pipe NAND terabit cell array transistor (TCAT) or vertical NAND (VNAND) used a concave damascene metal gate. Another vertical channel NAND string used a trench instead of a punched through-hole structure to make a square-wave shaped BL cell array transistor (SB-CAT). A series of vertical pipe floating gate (FG) NAND cells were also developed: the extended sidewall control gate (ESCG) cell, the separated sidewall control gate (S-SCG), the dual control gate with surrounding floating gate (DC-SF) cell with metal control gate last (MCGL), and the sidewall control pillar NAND flash cell. All of these vertical channel floating gate NAND flash cells had a polysilicon core and cylindrical floating gate with various types of sidewall control gates. A 3D vertical gate NAND flash array with stacked lateral bit-line layers and GAA NAND strings was discussed. Several evolutions were described of a 3D double-gate NAND array with lateral bit-lines, which used a junctionless thin-film transistor (TFT) BE-SONOS NAND technology. In one version, PN diode decoding eliminated multiple string select transistors in the array. Another version used multiple island gate decoding. A version was shown with a split page bit-line. Variability was modeled for the vertical gate NAND flash and gate-induced grain barrier lowering (GIGBL) and drain-induced grain barrier lowering (DIGBL) were introduced as grain boundary effects. A layer-by-layer etch technology was described for achieving a more vertical gate etch. A p-channel bit-line version of this vertical gate NAND flash was described along with a bit-alterable dual channel 3D vertical gate NAND flash array with both n-channel and p-channel characteristics. An array decoding method was described for this device.